(a) Field of the Invention
The present invention relates to a thin film transistor array panel for a liquid crystal display and a method for manufacturing the same, especially to a method for manufacturing a thin film transistor array panel with a reduced number of photolithography steps.
(b) Description of the Related Art
A liquid crystal display (LCD) is one of the most popular FPDs (flat panel displays). The LCD has two panels having electrodes for generating electric fields and a liquid crystal layer interposed therebetween. The transmittance of incident light is controlled by the intensity of the electric field applied to the liquid crystal layer.
In the most widely used LCD, the field-generating electrodes are provided at both panels, and one of the panels has switching elements such as thin film transistors (TFTs).
In general, a thin film transistor array panel is manufactured by photolithography using a plurality of photomasks, and five or six photolithography steps are used. The high cost for the photolithography process makes it desirable to reduce the number of the photolithography steps. Even though a few manufacturing methods using only four photolithography steps are suggested, these methods are not easy to accomplish.
Now, a conventional method of manufacturing a thin film transistor array panel using four lithography steps will be described.
First, a gate wire of aluminum or aluminum alloy are formed on a substrate by using a first mask. A gate insulating layer, an amorphous silicon layer, an n+ amorphous silicon layer and a metal layer are sequentially deposited. The metal layer, the n+ amorphous silicon and the amorphous silicon layer are patterned by using a second mask. At this time, gate pads of the gate wire is covered only with the gate insulating layer. An ITO (indium tin oxide) layer is deposited and patterned by using a third mask. At this time, the portions of the ITO layer over the gate pads are removed. After the metal layer and the n+ amorphous silicon layer thereunder are patterned by using the patterned ITO layer as an etch mask, a passivation layer is deposited. A complete thin film transistor array panel is obtained by patterning the passivation layer and gate insulating layer thereunder using a fourth mask, thereby removing the portion of the passivation layer and the gate insulating layer on the gate pads.
As a result, the gate pads of aluminum or aluminum alloy are exposed in the conventional manufacturing method of using four masks. The aluminum and the aluminum alloy cannot stand against physical and chemical variations and are vulnerable to damage and oxidation, despite their advantages of low resistivity. To compensate this matter, gate lines are formed to have multiple-layered structure or made of materials that can stand against the physical and chemical changes. However, the former makes the manufacturing process complicated, and the latter may result in a high resistivity problem.